DocumentCode :
3589278
Title :
An efficient layout decomposition approach for Triple Patterning Lithography
Author :
Jian Kuang ; Young, Evangeline F. Y.
Author_Institution :
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China
fYear :
2013
Firstpage :
1
Lastpage :
6
Abstract :
Triple Patterning Lithography (TPL) is widely recognized as a promising solution for 14/10nm technology node. In this paper, we propose an efficient layout decomposition approach for TPL, with the objective to minimize the number of conflicts and stitches. Based on our analysis of actual benchmarks, we found that the whole layout can be reduced into several types of small feature clusters, by some simplification methods, and the small clusters can be solved very efficiently. We also present a new stitch finding algorithm to find all possible legal stitch positions in TPL. Experimental results show that the proposed approach is very effective in practice, which can achieve significant reduction of manufacturing cost, compared to the previous work.
Keywords :
graph colouring; integrated circuit layout; lithography; efficient layout decomposition; legal stitch position; simplification method; small feature cluster; triple patterning lithography; Bridges; Color; Law; Layout; Libraries; Lithography; Layout Decomposition; Manufacturability; Triple Patterning Lithography;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
ISSN :
0738-100X
Type :
conf
Filename :
6560662
Link To Document :
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