Virtual shared memory for the ARAM model of computation using the MP1 packet routing chip

The author shows how virtual shared memory computers may be constructed from the MP1 communications chip for the ARAM computational model. He suggests solutions to the key issues of load-balancing and latency hiding. He favours the ARAM model interface as it provides a low bandwidth interface to the local processor, avoiding a direct coupling to the address lines of the processor and the low-latency scheduling that would be required of the processor in order to implement a PRAM model. For the ARAM model one may also adopt a strategy of stochastic mapping only when the compiler is unable to detect good static data distribution with balanced loads