Dual MAC processor for adaptive control of multiple high switching frequency DC-DC converters

This paper proposes a dual MAC (multiply-accumulator) processor for implementation of digital control algorithms to meet the demands of multiple high switching frequency power converters. An analysis of an adaptive digital power control algorithm illustrates the independence of certain operations in the algorithm and identifies a hardware structure that takes advantage of this. The architectural structure permits simultaneous operations to be executed, which leads to reduced algorithm execution time. The processor is governed by a set of instructions that allow the algorithms to be executed in a minimal number of clock cycles. The increased processor area compared with the traditional single MAC architecture is justified by the efficiency in resource utilisation and increased performance. Details of the optimised architecture are presented highlighting how the processor achieves increased performance by means of its characteristic hardware structure. Issues pertaining to both computational and data-storage elements are addressed.