DocumentCode
3590653
Title
Self-adaptive harris corner detector on heterogeneous many-core processor
Author
Paul, Johny ; Stechele, Walter ; Sousa, Ericles ; Lari, Vahid ; Hannig, Frank ; Teich, Jurgen ; Krohnert, Manfred ; Asfour, Tamim
Author_Institution
Inst. for Integrated Syst., Tech. Univ. of Munich, Munich, Germany
fYear
2014
Firstpage
1
Lastpage
8
Abstract
The recent years have shown the emergence of heterogeneous system architecture (HSA), which offers massive computational power assembled into a compact design. Computer vision applications with massive inherent parallelism highly benefits from such heterogeneous processors with on-chip CPU and GPU units. The highly parallel and compute intensive parts of the application program can be mapped to the GPU while the control flow and high level tasks may run on the CPU. However, they pose considerable challenge to software development due to their hybrid architecture. Sharing of resources (GPU or CPU) among applications running concurrently, leads to variations in processing interval and prolonged processing intervals leads to low quality results (frame drops) for computer vision algorithms. In this work, we propose resource-awareness and self organisation within the application layer to adapt to available resources on the heterogeneous processor. The benefits of the new model is demonstrated using a widely used computer vision algorithm called Harris corner detector. A resource-aware runtime-system and a heterogeneous processor were used for evaluation and the results indicate a well constrained processing interval and reduced frame-drops. Our evaluations demonstrate up to 20% improvements in processing rate and accuracy of the detected corner points for Harris corner detection.
Keywords
computer vision; edge detection; graphics processing units; microprocessor chips; multiprocessing systems; resource allocation; HSA; computer vision applications; heterogeneous many-core processor; heterogeneous system architecture; on-chip CPU units; on-chip GPU units; processing intervals; resource sharing; resource-aware runtime-system; resource-awareness; self organisation; self-adaptive Harris corner detector; software development; Central Processing Unit; Computer architecture; Detectors; Graphics processing units; Hardware; Parallel processing; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Architectures for Signal and Image Processing (DASIP), 2014 Conference on
Type
conf
DOI
10.1109/DASIP.2014.7115616
Filename
7115616
Link To Document