• DocumentCode
    3591098
  • Title

    Scaling graph community detection on the Tilera many-core architecture

  • Author

    Chavarria-Miranda, Daniel ; Halappanavar, Mahantesh ; Kalyanaraman, Ananth

  • Author_Institution
    High Performance Comput., Pacific Northwest Nat. Lab., Richland, WA, USA
  • fYear
    2014
  • Firstpage
    1
  • Lastpage
    11
  • Abstract
    In an era when power constraints and data movement are proving to be significant barriers for the application of high-end computing, the Tilera many-core architecture offers a low-power platform exhibiting many important characteristics of future systems, including a large number of simple cores, a sophisticated network-on-chip, and fine-grained control over memory and caching policies. While this emerging architecture has been previously studied for structured compute-intensive kernels, benchmarking the platform for data-bound, irregular applications present significant challenges that have remained unexplored. Community detection is an advanced prototypical graph-theoretic operation with applications in numerous scientific domains including life sciences, cyber security, and power systems. In this work, we explore multiple design strategies toward developing a scalable tool for community detection on the Tilera platform. Using several memory layout and work scheduling techniques we demonstrate speedups of up to 47× on 36 cores of the Tilera TileGX36 platform over the best serial implementation, and also show results that have comparable quality and performance to mainstream x86 platforms. To the best of our knowledge this is the first work addressing graph algorithms on the Tilera platform. This study demonstrates that through careful design space exploration, low-power many-core platforms like Tilera can be effectively exploited for graph algorithms that embody all the essential characteristics of an irregular application.
  • Keywords
    cache storage; computer architecture; graph theory; multiprocessing systems; Tilera TileGX36 platform; Tilera many-core architecture; caching policies; data movement; graph theory; high-end computing; low-power platform; memory policies; power constraints; scaling graph community detection; structured compute-intensive kernels; Communities; Convergence; Image color analysis; Layout; Multicore processing; Resource management; Tilera; community detection; graph algorithms; many-core; parallel;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing (HiPC), 2014 21st International Conference on
  • Print_ISBN
    978-1-4799-5975-4
  • Type

    conf

  • DOI
    10.1109/HiPC.2014.7116708
  • Filename
    7116708