Silent Sharing: An Efficient Mechanism to Fast Sequential Program Execution on Chip Multicore Processor

Chip Multicore processor provides new opportunity to fast sequential program performance with the available duplicated hardware resources in the cores. Most of existed sequential programs can benefit from a larger instruction window and a bigger L2 cache. In this paper, we propose a simple mechanism, Silent Sharing, to faster sequential program execution on a chip multicore processor. The basic idea is to send long latency instructions in the instruction window to the windows in other cores, as well as evicted blocks from local L2 to the free blocks in remote L2s in order to get a relative bigger instruction window and L2 storage. All the transfer operations are not viewable by the running program. In other words, a running core can silently share other available hardware resources in the other cores on the same chip. The hardware budget of our method is small, and the implementation is trivial. The initial analysis tells us that it is a promising way to improve sequential program performance in a chip multicore processor.