Title :
Thermal analysis and modeling of 3D integrated circuits for test scheduling
Author :
Rawat, Indira ; Gupta, M.K. ; Singh, V.
Author_Institution :
Dept. of Electr. Eng., Gov. Eng. Coll., Ajmer, India
Abstract :
A lot of present research is being devoted to the adoption of a new technology called 3D integration. The demand of today is also to enable the heterogeneous integration of different technologies so that a true SoC design can be realised. The technology poses several problems, the prominent ones being the removal of heat. The testing issue also comes into picture. One of the possible solutions to the problems can be the spliting of the inner stacks into more than one group and testing of these first so as to take advantage of low ambient temperature in the beginning of testing. The floorplan has been adjusted and the effect on temperature studied.
Keywords :
integrated circuit layout; integrated circuit modelling; integrated circuit packaging; integrated circuit testing; system-on-chip; thermal analysis; thermal management (packaging); 3D integrated circuits; 3D integration; SoC design; floorplan; heterogeneous integration; inner stack; low ambient temperature; test scheduling; thermal analysis; thermal modeling; Heating; Integrated circuit interconnections; Integrated circuit modeling; System-on-chip; Testing; Thermal analysis; Three-dimensional displays;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2013 IEEE International
DOI :
10.1109/3DIC.2013.6702374
