Wafer thinning for 3D integration

We are fast approaching the limits of what can be achieved by shrinking IC groundrules. Moore´s Law, which states that the number of transistors on an integrated circuit doubles approximately every two years, is no longer true. Transistor counts are expected to increase at a slower pace for the next few years, doubling only every three years or so. In light of this decreasing trend, the increase in functionality can be expected to come from a combination of transistor count and packing density - 3D chip stacking or 3D packaging. Since the thinner the die, the more die can be stacked per unit volume, a common thread through virtually all modern packing processes is wafer thinning. We will discuss an all-chemical wafer thinning process (WaveEtch™) that is inexpensive, single-sided, and that is compatible with wafer thickness of down to 40 μm, or less. The WaveEtch™ process effectively decouples chemistry from transport phenomena, thus increasing uniformity and providing greater flexibility in working with novel chemistries. Aside from blanket thinning, it can also create unique final surface textures on scales of nanometers to micrometers. The tools´ design allows for uniform etching of nearly any substrate type and material; from round to rectangular, for semiconductor, optical, and solar applications.