• DocumentCode
    3592285
  • Title

    A 40nm fully functional SRAM with BL swing and WL pulse measurement scheme for eliminating a need for additional sensing tolerance margins

  • Author

    Chen, Yen-Huei ; Chou, Shao-Yu ; Lee, Quincy ; Chan, Wei-Min ; Sun, Dar ; Liao, Hung-Jen ; Wang, Ping ; Chang, Meng-Fan ; Yamauchi, Hiroyuki

  • Author_Institution
    TSMC, Hsinchu, Taiwan
  • fYear
    2011
  • Firstpage
    70
  • Lastpage
    71
  • Abstract
    A method for direct measurements of bit-line (BL) swing, sense amplifier (SA) offset and word-line (WL) pulse width is demonstrated in a 40nm CMOS 32kb fully functional SRAM macro with <;2% area penalty. This allows, for the first time, deciding the best tuning option for WL-pulse (WLP) width based on the results being measured on site for BL swing and dynamic read/write stability (DRWS), which both depend on WLP width. It has enabled to eliminate a need of additional margin for BL swing, which was conventionally needed for ensuring tolerance against its simulation errors and inaccurate SA-offset estimation. As a result, it was found that more aggressive option for WLP width could be chosen while ensuring the target BL swing.
  • Keywords
    CMOS memory circuits; SRAM chips; amplifiers; pulse measurement; CMOS; bit-line swing; dynamic read-write stability; fully functional SRAM; memory size 32 KByte; sense amplifier offset; sense amplifier-offset estimation; sensing tolerance margins; size 40 nm; tuning option; word-line pulse measurement scheme; world-line-pulse width; Area measurement; Current measurement; Data models; Frequency measurement; Random access memory; Time measurement; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2011 Symposium on
  • ISSN
    2158-5601
  • Print_ISBN
    978-1-61284-175-5
  • Type

    conf

  • Filename
    5986219