A software tool for the timing analysis of embedded software

The presence of real-time software modules which interact with specific hardware architectures is growing in today´s embedded applications. New methods and tools are needed for program analysis and the validation of these designs. The timing analysis of software is an essential aspect because real-time requirements need to be validated and because performance objectives could be missed if the software design does not fit with the hardware design. In this paper, we describe a new timing analysis for software which is executed on architectures with a one-level instruction cache. The safety of the timing estimates is guaranteed by this method, and the accuracy can be traded off against the processing time. The implementation details of the related software tool are reported, and the practical use of the tool is shown by some experimental results.