A synthesis approach for the generation of parallel architectures

This paper presents a new process for synthesizing multiprocessor architectures. A behavioral partitioning phase is proposed to build the parallel architecture, before actual synthesis. This partitioning concerns both data and operations which allows exploiting more parallelism. The input specification uses a functional language, proposed for arrays, which allows to elegantly partition data. The output specification is a behavioral description of the architecture (processors, communication, data) in VHDL or in parallel code. Hence, this methodology fits into the general framework of hardware/software design. It fills a gap between parallel machine compilers and high level synthesis systems. A mixture of many techniques relevant to high level synthesis and parallel compilation have been adopted, such as ASAP-ALAP scheduling, rate-optimal scheduling, and clustering. Hence, a more general technique is proposed, Our technique provides much better results than the commonly used nested loop schedules