Adaptive trimming test approach — The efficient way on trimming analog trimmed devices at wafer sort

In this paper, we have performed an empirical evaluation of several analog trimming methodologies used for Semiconductor Manufacturing Wafer Sort testing. The study shows that a dynamic trimming approach is the best among those evaluated. The other methodologies evaluated in this paper suffer for several weaknesses such as: 1) unwanted yield loss when the actual least significant bit (LSB) equivalent value or weight drifts from the characterized value due to fab process variations, 2) higher test time leading to elevated cost of test and delivery cycle time degradation, and 3) continual need for Test Program modifications to account for fab process shifts. Finally, a review of basic trimming principles will be covered. We will discuss the need for parameter trimming in the semiconductor industry along with common analog trimming algorithms and review actual wafer test data at wafer probe.