Single-sided cap solution for thinner Z-height

Efforts to enable a more cost-effective power integrity (PI) solutions to cater for the needs of emerging markets are described in this paper. The challenge in the PI design is compounded by the requirements of low system cost and z-height, i.e. high density interconnect (HDI) boards and backside capacitors (BSC) are not viable options. And to enable low profile packages, no package decoupling capacitors are employed; thus, adding to the requirements for better onboard decoupling. Techniques to reduce the impedance profile from system on chip (SoC) to the Power management integrated circuit (PMIC) will be addressed. While the principles in the following sections are applicable to both Core and I/O circuits, the scope of the results are on Core and the decoupling frequency of interest is in the MHz range.