Analyzing package-on-package (PoP) reflow assembly interfaces with interconnect gap analysis

The product design and manufacturing processes related to package-on-package (PoP) devices continue to evolve, driven by the needs of mobile device OEMs and their end-user customers. Trends in the semiconductor industry are driving PoP assemblies to be thinner and smaller, while containing more interconnects than ever before. As the components that constitute a PoP device become thinner, with smaller-pitch solder joints, dynamic warpage during the reflow process has more potential to cause problems such as Head-in-Pillow and non-wet opens. This paper presents the latest technology for analyzing the compatibility of the assembled components to predict how well they will reliably solder, by evaluating how well their shapes match at each critical temperature throughout the reflow profile.