A systolic memory architecture for fast codebook design based on MMPDCL algorithm

Vector quantization with an adaptive codebook is attractive for lossy data compression. During the last few decades, architectures have been proposed to accelerate adaptive codebook design that requires a huge amount of computation. However, they are mainly based on Kohonen competitive learning algorithm or LBG algorithms that have an essential problem, the under-utilization problem. This paper presents a systolic memory architecture for highspeed codebook design based on MMPDCL algorithm not suffering from the under-utilization problem. We modify MMPDCL algorithm to exploit parallelism and implement with simple hardware. Simulation results demonstrated that the modified MMPDCL algorithm can give codebooks with comparable MSEs to the original MMPDCL algorithm.