Title :
A fault simulation based test pattern generator for synchronous sequential circuits
Author :
Guo, Ruifeng ; Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fDate :
6/21/1905 12:00:00 AM
Abstract :
We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures
Keywords :
automatic test pattern generation; circuit simulation; computational complexity; fault simulation; logic testing; sequential circuits; computational complexity; fault coverages; fault simulation; run times; synchronous sequential circuits; test pattern generator; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Genetics; Logic testing; Sequential analysis; Sequential circuits; Synchronous generators; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Print_ISBN :
0-7695-0146-X
DOI :
10.1109/VTEST.1999.766674
