Title :
A logic CMOS compatible Flash EEPROM for small scale integration
Author :
Shalchian, Majid ; Atarodi, S. Mojtaba
Author_Institution :
Electr. Eng. Dept., Sharif Univ. of Technol., Tehran, Iran
Abstract :
A single-poly floating gate non volatile memory cell is presented. In this device the second poly layer is removed to make the device compatible with standard logic CMOS process. An array of cells with high storage density has been fabricated on a standard 0.25 μm CMOS process with a special architecture. All memory cells tolerate 60000 cycles of endurance test and show 10 years of data retention. Using this cell, a small to medium size (typically 64 K*8b) Flash EEPROM array would be integrated in standard logic CMOS process.
Keywords :
CMOS logic circuits; CMOS memory circuits; MOS capacitors; MOSFET; flash memories; logic arrays; oxidation; semiconductor growth; 0.25 micron; MOS capacitors; MOSFET; data retention; endurance test; logic CMOS compatible flash EEPROM; oxidation; single-polyfloating gate nonvolatile memory cell; small scale integration; storage density; CMOS logic circuits; CMOS process; CMOS technology; Capacitors; Doping; EPROM; Fabrication; Geometry; Logic devices; Nonvolatile memory;
Conference_Titel :
Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on
Print_ISBN :
977-05-2010-1
DOI :
10.1109/ICM.2003.1287829
