High-speed compiled-code simulation of transition faults

A highly efficient approach is presented for simulating transition faults in combinational logic for the generation of transition fault test patterns. The high performance is gained by parallel pattern compiler-driven simulation techniques together with a novel analyzing algorithm. This algorithm achieves a high efficiency by exploiting all parallel patterns by examining all possible pairs of pattern combinations to detect a transition fault. The simulation method and the results of the ISCAS benchmark circuits are presented and show a significant increase in speed for the generation of transition fault test patterns with random patterns.<>