Title :
The development of iHARP: a multiple instruction issue processor chip
Author :
Steven, G.B. ; Adams, R.G. ; Findlay, P.A. ; Trainis, S.A.
Author_Institution :
Hatfield Polytech., UK
fDate :
11/4/1991 12:00:00 AM
Abstract :
The objective of the HARP project is to design, build and test a processor which executes non-numeric benchmarks at a sustained execution rate in excess of two instructions per cycle. Earlier work at Hatfield centered around the design of an abstract HARP architectural model. This paper describes iHARP, a physical realisation of the HARP architectural model within the constraints of a single VLSI chip
Keywords :
microprocessor chips; reduced instruction set computing; HARP architectural model; HARP project; VLSI chip; iHARP; non-numeric benchmarks;
Conference_Titel :
RISC Architectures and Applications, IEE Colloquium on
