DocumentCode :
3594586
Title :
RF substrate noise characterization for CMOS 0.18 μm
Author :
Ishak, Izahan Syemylona ; Keating, Richard Alan ; Chakrabarty, Chandan K.
Author_Institution :
Process Integration Dept., Kulim, Malaysia
fYear :
2004
Firstpage :
60
Lastpage :
63
Abstract :
In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the deep nwell (or triple well isolation) and the P+ guard ring. The test structures were designed and fabricated using Silterra CMOS 0.18 μm mixed signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (Sout) in which the substrate coupling effects with and without deep nwell were characterized.
Keywords :
CMOS integrated circuits; electromagnetic coupling; integrated circuit noise; isolation technology; mixed analogue-digital integrated circuits; semiconductor device noise; substrates; 0.18 micron; CMOS mixed signal process; P+ guard ring; RF substrate noise characterization; Silterra CMOS; deep nwell; isolation ring distance; on-chip RF isolation techniques; output terminal; submicron technologies; substrate coupling effects; triple well isolation; CMOS process; CMOS technology; Circuit noise; Circuit testing; Conductivity; Diodes; Isolation technology; Radio frequency; Silicon; Working environment noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
RF and Microwave Conference, 2004. RFM 2004. Proceedings
Print_ISBN :
0-7803-8671-X
Type :
conf
DOI :
10.1109/RFM.2004.1411075
Filename :
1411075
Link To Document :
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