Mismatch Compensated Design Techniques under Packaging-Induced Die Stress

Mismatch behavior under packaging-induced die stress is presented. The mobility shift caused by package stress is a dominant source of analog circuit mismatch. Shallow trench isolation (STI) and well proximity effect (WPE) are also significant contributors to the mismatch in deep submicron CMOS technology. The experimental results performed with current steering 12-bit 90-nm CMOS I/Q digital-to-analog converter (I/Q DAC) having 150-mum die thickness well agree to the theory developed in this paper. The theoretical and experimental results also provide design guidance for minimizing the mismatch of analog circuits to packaging-induced die stress.