Title :
Mismatch Compensated Design Techniques under Packaging-Induced Die Stress
Author :
Seo, Dongwon ; Guo, Yuhua
Author_Institution :
Qualcomm Inc., San Diego, CA
Abstract :
Mismatch behavior under packaging-induced die stress is presented. The mobility shift caused by package stress is a dominant source of analog circuit mismatch. Shallow trench isolation (STI) and well proximity effect (WPE) are also significant contributors to the mismatch in deep submicron CMOS technology. The experimental results performed with current steering 12-bit 90-nm CMOS I/Q digital-to-analog converter (I/Q DAC) having 150-mum die thickness well agree to the theory developed in this paper. The theoretical and experimental results also provide design guidance for minimizing the mismatch of analog circuits to packaging-induced die stress.
Keywords :
CMOS analogue integrated circuits; digital-analogue conversion; integrated circuit packaging; isolation technology; stress effects; 120 bit; 150 micron; 90 nm; CMOS technology; analog circuit mismatch; digital-to-analog converter; mismatch compensated design techniques; packaging-induced die stress; shallow trench isolation; well proximity effect; Analog circuits; Analog-digital conversion; CMOS technology; Digital-analog conversion; Integrated circuit manufacture; Integrated circuit packaging; Integrated circuit technology; Isolation technology; Proximity effect; Stress;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378786
