Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands

Voltage islands provide a very good opportunity for minimizing the energy consumption of core-based Networks-on-Chip (NoC) design by utilizing a unique supply voltage for the cores on each island. This paper addresses various complex design issues for NoC implementation with voltage islands. A novel design framework based on genetic algorithm is proposed to optimize both the computation and communication energy with the creation of voltage islands concurrently for the NoC using multiple supply voltages. The algorithm automatically performs tile mapping, routing path allocation, link speed assignment, voltage island partitioning and voltage assignment simultaneously. Experiments using both real-life and artificial benchmarks were performed and results show that, by using the proposed scheme, significant energy reduction is obtained.