Title :
OPC-Free and Minimally Irregular IC Design Style
Author :
Maly, W. ; Lin, Yi-Wei ; Marek-Sadowska, M.
Author_Institution :
CMU, Pittsburgh
Abstract :
Advancements in IC manufacturing technologies allow for building very large devices with billions of transistors and with complex interactions between them encapsulated in a huge number of design rules. To ease designers´ efforts in dealing with electrical and manufacturing problems, regular layout style seems to be a viable option. In this paper we analyze regular layouts in an IC manufacturability context and define their desired properties. We introduce the OPC-free IC design methodology and study properties of cells designed for this layout style that have various degrees of regularity.
Keywords :
VLSI; design for manufacture; integrated circuit layout; integrated circuit manufacture; proximity effect (lithography); IC layout; IC manufacturability; OPC-free IC design; VLSI; layout style; transistors; Buildings; Costs; Design for manufacture; Integrated circuit layout; Integrated circuit modeling; Integrated circuit technology; Investments; Manufacturing; Shape; Transistors; DFM; IC layout regularity; OPC-free; Performance; VLSI; advanced technology; design; design paradigm; economics; manufacturability; multiple exposure;
Conference_Titel :
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Print_ISBN :
978-1-59593-627-1
