Title :
Performance comparison of bulk and SOI planar junctionless SONOS memory
Author :
Lodhi, Rajesh Singh ; Pandey, Som Dutt ; Sahu, Chitrakant ; Singh, Jawar
Author_Institution :
PDPM, Indian Inst. of Inf. Technol., Jabalpur, Jabalpur, India
Abstract :
In this paper, we have demonstrated the performance analysis of a planar junctionless (JL) silicon-oxide-nitride-oxide-silicon (SONOS) memory cell implemented on the bulk and silicon-on-insulator (SOI) substrate wafer. Both cells are simulated using extensive two dimensional device simulator and compared on the basis of improved memory characteristics. The JL SOI SONOS exhibits larger memory window within a specified programming time as compared with the JL bulk type. The erasing efficiency of the JL bulk SONOS is better due to incorporation of carriers from the substrate end and it also has the advantage of tunable channel layer that can be controlled by substrate doping.
Keywords :
integrated circuit modelling; random-access storage; silicon-on-insulator; substrates; JL SOI SONOS; SOI substrate wafer; SONOS memory cell; bulk substrate wafer; erasing efficiency; extensive two dimensional device simulator; planar junctionless silicon-oxide-nitride-oxide-silicon memory cell; silicon-on-insulator substrate wafer; specified programming time; substrate doping; tunable channel layer; Charge carrier processes; Doping; Logic gates; Programming; SONOS devices; Silicon; Substrates; 2-D simulation; Bulk; Junctionless (JL) memory; Silicon-On-Insulator (SOI); Silicon-OxideNitride-Oxide-Silicon (SONOS);
Conference_Titel :
Emerging Electronics (ICEE), 2014 IEEE 2nd International Conference on
Print_ISBN :
978-1-4673-6527-7
DOI :
10.1109/ICEmElec.2014.7151210
