Performance of different topologies for three level inverter based on space vector pulse width modulation technique

Multilevel inverters are progressively being used in high-power medium voltage energy control industrial drive applications due to their superior performance compared to conventional two-level inverters. There are a number of topologies applied in recent years. The most widely applied topologies are Diode Clamped Inverter (DCLI), Capacitor Clamped Inverter (CCLI) and Cascaded H-Bridge Inverter (CHBI). Three level DCLI requires additional 6 clamping diodes and CCLI requires 3 clamping capacitors that make the system bulky and quite difficult to implement while increasing the number of level. CHBI requires no additional diodes or capacitors and it is easy to implement. But it requires 2 DC sources that increases the system cost. In this paper, these three topologies for three level inverter using space vector pulse width modulation (SVPWM) technique has been modelled and simulated using MATLAB/SIMULINK and Origin 6.1 for a passive R-L load. From the simulation results, CHBI with separate DC source (CHBISEDCS) shows the better performance to the others in terms of THD. CHBI using single DC (CHBISDC) source is also presented and compared with CHBISEDC. CHBISDC shows better performance without significant increase of THD compared to CHBISEDC. Hence CHBISDC minimizes the system cost and provides better performance.