3D-enabled customizable embedded computer (3DECC)

Author

Franzon, Paul D. ; Rotenberg, Eric ; Tuck, James ; Huiyang Zhou ; Davis, W. Rhett ; Hongwen Dai ; Joonmoo Huh ; Sunkgwan Ku ; Lipa, Steve ; Chao Li ; Park, Jong Beom ; Schabel, Joshua

Author_Institution

Dept. of ECE, North Carolina State Univ., Raleigh, NC, USA

fYear

2014

Firstpage

1

Lastpage

3

Abstract

This paper describes a 3D computer architecture designed to achieve the lowest possible power consumption for “embedded applications” like radar and signal processing. It introduces several unique concepts including a low-power SIMD tile, low-power 3D memories, and 3D and 2.5D interconnect that is circuit switched so it can be tuned at run-time for a specific application. When conservatively projected to the 7 nm node, simulations of the architecture show potential for exceeding 75 GFLOPS/W, about 20x better than today´s CPUs and GPUs. This translates to 13 pJ/FLOP. This paper will focus on the 3D specific aspects of the design. This architecture is highly suited to DSP and multimedia workflows.

Keywords

embedded systems; integrated circuit design; integrated circuit interconnections; low-power electronics; parallel processing; random-access storage; three-dimensional integrated circuits; 2.5D interconnect; 3D computer architecture; 3D interconnect; 3DECC; DSP; embedded applications; low-power 3D memories; low-power SIMD tile; multimedia workflows; power consumption; radar processing; signal processing; size 7 nm; Benchmark testing; Computer architecture; Integrated circuit interconnections; Power demand; Random access memory; Switching circuits; Three-dimensional displays; 2.5D; 3DIC; SIMD; low-power CPU; low-power GPU; low-power MPI; radar processing;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2014 International

Type

conf

DOI

10.1109/3DIC.2014.7152143

Filename

7152143