Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges

Author

De Vos, Joeri ; Cherman, Vladimir ; Detalle, Mikael ; Teng Wang ; Salahouelhadj, Abdellah ; Daily, Robert ; Van der Plas, Geert ; Beyne, Eric

Author_Institution

Imec, Heverlee, Belgium

fYear

2014

Firstpage

1

Lastpage

7

Abstract

3D stacked IC (SIC) vs. 3D Interposer wafer processing and assembly challenges are discussed in this paper. We report on the key enabling technologies like wafer thinning, thin wafer handling, TSV, micro bumping, package bumping, stacking and packaging. The limited micro bump yield loss in the 3D SIC case is explained by modeling of bonding force distribution. It is also shown that for sequential stacking a NiB cap of the Cu micro bumps is heavily increasing stacking yield.

Keywords

copper; integrated circuit modelling; integrated circuit packaging; nickel compounds; three-dimensional integrated circuits; wafer bonding; 3D SIC; 3D interposer integration; 3D stacked IC; Cu; NiB; TSV; assembly challenge; bonding force distribution modeling; integrated circuit packaging; microbump yield loss; package bumping; thin wafer handling; through silicon via; wafer processing; wafer thinning; Bonding; CMOS integrated circuits; Packaging; Passivation; Silicon carbide; Stacking; Three-dimensional displays; 3D; NiB capping layer; interposer; packaging; processing;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2014 International

Type

conf

DOI

10.1109/3DIC.2014.7152146

Filename

7152146