Title :
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration
Author :
Bui Thanh Tung ; Xiaojin Cheng ; Watanabe, Naoya ; Kato, Fumiki ; Kikuchi, Katsuya ; Aoyagi, Masahiro
Author_Institution :
Nanoelectron. Res. Inst., Tsukuba, Japan
Abstract :
In this paper, investigation of Parylene-HT for using as insulation/liner in through-silicon-via (TSV) is presented. Bottom-up copper filled TSVs with 1 μm Parylene-HT insulator with aspect ratios (ARs) up to 10, are demonstrated on a 100 μm-thick Si wafer through via etching, parylene vapor deposition, and copper electroplating processes. Cross sectional inspections on the fabricated TSVs confirm the pin-hole free, high-uniformity, good conformal coverage room temperature deposited Parylene-HT liner, the void- and seam-free filled Cu, as well as the low diffusivity of Cu into Parylene-HT. Excellent insulation function of Parylene-HT liner, i.e., capacitance of 0.164 pF/TSV and leakage current density of 22 pA/cm2 at a field of 0.25 MV/cm, were also confirmed on the fabricated TSV. As the Parylene-HT deposition and Cu electroplating processes can be implemented at room temperature, the copper filled TSV formation with Parylene-HT insulator investigated in this work is highly compatible with low-temperature 3D integration.
Keywords :
copper; electroplating; elemental semiconductors; etching; integrated circuit interconnections; silicon; three-dimensional integrated circuits; vias; Cu; Si; copper electroplating process; copper filled TSV formation; cross sectional inspection; etching; low-temperature 3D integration; parylene vapor deposition; parylene-HT insulator; pin-hole free; size 1 mum; size 100 mum; through-silicon-via; Capacitance; Copper; Fabrication; Insulators; Silicon; Three-dimensional displays; Through-silicon vias; 3D integration; Parylene-HT; TSV; TSV liner;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2014 International
DOI :
10.1109/3DIC.2014.7152162
