Analysis of thermal stress distribution for TSV with novel structure

Through Silicon Via (TSV) plays a key role in accomplishing 3D IC integration. In most common approaches, TSV is filled with copper. Due to large mismatch in Coefficients of Thermal Expansion (CTE) between the copper via and the silicon of TSV, significant thermal stresses will be induced at the interfaces of Cu/dielectric layer (usually SiO₂) and dielectric layer/Si, which would lead to various reliability and electrical performance issues. As a solution, a novel structure TSV (Annular-Trench-Isolated TSV: ATI TSV) was proposed to optimize the thermal stress distribution. A ring of Si is remained between Cu and SiO₂ during print process. The better thermal properties of ATI TSV was revealed by Finite Element Method simulation. The thermal stress level of ATI TSV is compared to most common cylindrical TSV (regular TSV) and annular TSV. Due to the large CTE mismatch between copper and silicon, the stress is concentrated at the interface of Cu/Si inside TSV under thermal load. In case of 5 μm TSV diameter, thermal stress with level of less than 30 MPa is achieved in silicon substrate of ATI TSV with 80% reduction comparing to regular TSV. The silicon ring thickness is constant as 1 μm in this study. With downsizing TSV diameter, the volume ratio of silicon ring to copper core increases. Therefore, the effect of stress concentration at the interface of Cu/Si inside TSV enhanced with TSV scaling down. Further reducation of stress in silicon substrate can be achieved by thicken silicon ring in ATI TSV.