Fault detection and isolation of multiple defects in through silicon via (TSV) channel

Through silicon via (TSV) based 3D-IC is the key technology to satisfy the continuously growing demand on lower power consumption, higher system bandwidth and smaller form factor of electronic devices. As the I/O count increases up to the order of tens of thousands for high speed data transmission, TSV diameter and interconnection pitch are reduced, which may cause various defects throughout the channel. In this paper, we present a fault detection and isolation method for multiple defects in TSV channel by analyzing the electrical characteristics in frequency- and time-domain. In TSV channels with 5-layer stacked dies, open and short defects are intentionally inserted in different locations and the electrical characteristics are analyzed by 3D FEM solver simulation. The type of defects can be distinguished by S₂₁ magnitude; by comparing S₁₁ and S₂₂ magnitude curves, the location of defects can be localized.