Leveraging 3D-IC for on-chip timing uncertainty measurements

Modern high-performance designs require accurate on-chip timing uncertainty measurements for post-silicon validation of high speed interfaces and clock distribution networks. On-chip timing measurements capabilities must keep up with growing design complexity and process variations to meet competitive product time-to-market. However, enhancing silicon debug capabilities cannot simply be met by proliferating on-chip structures, since the overhead would be prohibitively expensive to deploy. We propose moving on-chip debug and validation structures onto a separate die which would be stacked onto the product die using three-dimensional integration (3D-IC). This paper focuses on achieving observability at clock sinks which are critical for understanding on-chip timing uncertainty. We present a circuit implementation and design flow which realizes high volume on-chip timing measurements for a 2D product die.