Low-complexity entirely-overlapped parallel decoder architecture for quasi-cyclic LDPC codes

In this paper, we propose a low-complexity entirely-overlapped partially-parallel decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. For a (c, t)-regular QC-LDPC decoder, this decoder can achieve approximate 100% hardware utilization efficiency (HUE) and entirely overlapped decoding by using only one check node process unit group (CNUG) to process c groups of check node messages sequentially. Compared with traditional partially-parallel decoder, the quantities of check node process unit (CNU), barrel shifters and counters can be decreased prominently. Moreover, it is flexible in code rate and code length.