Experimental characterization and model validation of thermal hot spots in 3D stacked ICs

3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnections. The major bottleneck for 3D integration are thermal management issues due to the reduced thermal spreading in the thinned dies and the poor thermally conductive adhesives. In this paper, a dedicated thermal test vehicle with integrated heaters and sensors is presented to experimentally characterize the thermal behavior in 3D stacks. This test vehicle is used to validate a presented methodology for fine grain thermal analysis in 3D-ICs.