ASIP micro-code generation from high-level specifications

Existing techniques in high-level synthesis mostly assume a simple controller model in the form of a single FSM. However, in reality more complex controller architectures are often used. On the other hand, in the case of programmable processors, the controller architecture is largely defined by the available control-flow instructions in the instruction set. This paper describes an important extension of an existing architectural synthesis system (AMICAL) targeting the generation of microcoded for ASIP controllers. The designer can then generate both style of architecture, hardwired and programmable, using the same synthesis system and can quickly evaluate the trade-offs of hardware decisions.