DocumentCode :
3598046
Title :
A block matching algorithm with 16:1 subsampling and its hardware design
Author :
Kim, Yanghoon ; Rim, Chong S. ; Min, Byoungki
Author_Institution :
Dept. of Comput. Sci., Sogang Univ., Seoul, South Korea
Volume :
1
fYear :
1995
Firstpage :
613
Abstract :
Conventional full search block matching algorithm (BMA) for motion estimation is computationally intensive and the resulting hardware cost is very high. In this paper, we present an efficient BMA using a 16:1 subsampling technique, and describe its hardware design. The algorithm reduces the number of pixels in calculating the mean absolute difference at each search location, instead of reducing the search locations. The algorithm is an extension of the BMA with 4:1 subsampling proposed by Lin and Zaccarin (1993) such that the amount of computation is reduced by a factor of 4 (16 compared to the full search BMA) while producing similar performance. The algorithm can efficiently be designed into a hardware for real-time applications
Keywords :
data compression; image matching; image processing equipment; image sampling; motion estimation; real-time systems; video coding; 16:1 subsampling; MPEG-1 encoding system; block matching algorithm; hardware design; motion estimation; real-time applications; Algorithm design and analysis; Encoding; Hardware; Labeling; Radio frequency;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Print_ISBN :
0-7803-2570-2
Type :
conf
DOI :
10.1109/ISCAS.1995.521588
Filename :
521588
Link To Document :
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