Title :
Mapping nested loops to field programmable gate array based systems
Author :
Spillane, John ; Jean, Jack S N
Author_Institution :
Wright Lab., Wright-Patterson AFB, OH, USA
Abstract :
The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) architecture is based on Xilinx 4000 series field programmable gate array (FPGA) devices. These devices make CHAMP a programmable hardware resource that can be used to process data in real time. Recently the task of mapping Reed-Solomon decoding onto the CHAMP architecture was undertaken. During the process of mapping a sequential `C´ code to CHAMP, problems related to implementing a highly data dependant algorithm on an FPGA based system were uncovered. One problem that was dealt with, and is examined in this paper is the mapping of nested loops to FPGAs. This paper also provides future directions for improving user interaction with the CHAMP system
Keywords :
Reed-Solomon codes; field programmable gate arrays; logic programming; program processors; reconfigurable architectures; CHAMP; Configurable Hardware Algorithm Mappable Preprocessor; Reed-Solomon decoding; Xilinx 4000 series; data dependant algorithm; field programmable gate array; mapping; nested loops; programmable hardware resource; real time; sequential C code mapping; user interaction; Application specific integrated circuits; Circuit testing; Computer architecture; Contracts; Decoding; Field programmable gate arrays; Hardware; Power engineering computing; Read-write memory; Reed-Solomon codes; Switches; System testing;
Conference_Titel :
Aerospace and Electronics Conference, 1995. NAECON 1995., Proceedings of the IEEE 1995 National
Print_ISBN :
0-7803-2666-0
DOI :
10.1109/NAECON.1995.521943
