• DocumentCode
    3598815
  • Title

    CMOS shallow trench isolation x-stress effect on channel width for 0.18μm technology

  • Author

    Tan, Philip Beow Yew ; Kordesch, A.V. ; Sidek, Othman

  • Author_Institution
    Silterra Malaysia Sdn., Kedah, Malaysia
  • Volume
    1
  • fYear
    2004
  • Firstpage
    319
  • Abstract
    We have investigated the effect of shallow trench isolation (STI) induced mechanical x-stress (in the direction of channel length) effect on transistor channel width. STI x-stress has less effect on narrow width NMOS transistor for both threshold voltage (Vt) and drain current (Id). For narrow width PMOS transistor, STI x-stress has higher effect on Id. PMOS Vt is not affected by STI x-stress.
  • Keywords
    CMOS integrated circuits; MOSFET; isolation technology; stress effects; 0.18 micron; CMOS; NMOS transistor; PMOS transistor; drain current; mechanical x-stress; shallow trench isolation; threshold voltage; transistor channel width; CMOS technology; Degradation; Electric variables; Fingers; Isolation technology; MOS devices; MOSFETs; Testing; Threshold voltage; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
  • Print_ISBN
    0-7803-8511-X
  • Type

    conf

  • DOI
    10.1109/ICSICT.2004.1435016
  • Filename
    1435016
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3598815