Title :
Driver modeling and alignment for worst-case delay noise
Author :
Sirichotiyakul, Supamas ; Blaauw, David ; Oh, Chanhee ; Levy, Rafi ; Zolotov, Vladimir ; Zuo, Jingyan
Author_Institution :
Motorola Inc., Austin, TX, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross coupling capacitance. The proposed model effectively captures the nonlinear behavior of the victim driver gate during the transition and has an average error below 8% whereas the traditional approach using a Thevenin model incurs an average error of 48%. We also discuss the worst case alignment of the aggressor net transitions with respect to the victim net transition, emphasizing the need to maximize not merely the delay of the interconnect alone but the combined delay of the interconnect and receiver gate. We show that the worst case alignment of an aggressor net transition is a function of the receiver gate output loading, victim transition edge rate, and the noise pulse width and height and hence propose a pre-characterization approach to efficiently predict the worst-case alignment. The proposed methods were implemented in an industrial noise analysis tool called ClariNet. Results on industrial designs are presented to demonstrate the effectiveness of our approach.
Keywords :
capacitance; circuit simulation; delays; driver circuits; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; ClariNet; aggressor net transitions; average error; cross coupling capacitance; cross-coupling noise; driver alignment; driver modeling; industrial noise analysis tool; interconnect delay; linear driver model; noise pulse; noise pulse width; nonlinear behavior; pre-characterization approach; receiver gate output loading; switching signal net; victim net transition; victim transition edge rate; worst case alignment; worst-case delay noise; Analytical models; Delay; Ear; Noise figure; Parasitic capacitance; Permission; Semiconductor device noise; Space vector pulse width modulation; Switches; Voltage;
Conference_Titel :
Design Automation Conference, 2001. Proceedings
Print_ISBN :
1-58113-297-2
DOI :
10.1109/DAC.2001.156231