Architectures and building blocks for CMOS VLSI analog `neural´ programmable optimizers

A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization algorithms with digital programmability of the problem weights. Area overhead due to programmability is reduced by using time multiplexing methodology. It allows all the weights of each multiple inputs processing unit to be digitally controlled by just using one weighted component array. The proposed architecture is very well suited for MOS VLSI realization using switched-capacitor (SC) techniques. SC schematics for the different building blocks are presented and demonstrated via empirical results