Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique

This paper presents a design approach for upgrading the resiliency of ultra-low-voltage (ULV) microprocessors through a voltage-scalable and low-overhead in-situ error detection and correction (EDAC) technique. Particular efforts are made to overcome the poor voltage scalability and area/energy/throughput overhead of the existing EDAC techniques when applied to ULV designs. The 16 bit microprocessor employing the proposed EDAC and dynamic voltage scaling schemes is demonstrated in a 65 nm. The microprocessor can automatically modulate VDD based on timing error flags across static/slow variations and in-situ detect and correct the timing errors from fast dynamic variations, virtually eliminating timing and voltage margins. At a typical process/voltage/temperature corner, the proposed design improves the minimum energy consumption by 42% with 140 mV additional voltage scaling, as compared to the baseline design. At the same throughput (80 MHz), the proposed design consumes 38% less energy than the baseline operating at its minimum energy point. At the same energy consumption, the proposed design achieves 2.3 × higher throughput than the baseline design. The area overhead of the proposed design is 8.3%.