DocumentCode
3599619
Title
Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG)
Author
Reddy, Basireddy Karunakar ; Sabbavarapu, Srinivas ; Acharyya, Amit
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol., Hyderabad, Hyderabad, India
fYear
2014
Firstpage
135
Lastpage
139
Abstract
In this paper, we propose two different algorithms for Shannon Factor Graph (SFG) construction, which can be used for cut-less mapping, to improve the runtime, graph size and required memory size. The first SFG construction algorithm does not consider the nature of the nodes (constant one and zero, non-decomposed and shared nodes) while building the SFG, whereas the second algorithm finds out the nature of the nodes on-the-fly. We observed that the constant one and zero, Shared and non-decomposed nodes can be used at the time of SFG construction to minimize the runtime and graph size significantly and to make the graph semi-canonical. The theoretical analysis and experiments performed on the standard benchmark circuits show that, by finding the constant one and zero, shared and non-decomposed nodes on-the-fly reduces the graph size by a factor of 126 and the runtime by a factor of 5.5.
Keywords
digital integrated circuits; integrated circuit design; SFG construction algorithm; Shannon factor graph; benchmark circuit; constant one node; cut-less mapping; digital IC design; graph size; logic synthesis; nondecomposed node; shared node; zero node; Benchmark testing; Boolean functions; Buildings; Libraries; Logic gates; Runtime; Standards; Cut-based technology mapping; Cut-enumeration; Cut-less technology mapping; Logic Synthesis; Shannon decomposition theorem;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic System Design (ISED), 2014 Fifth International Symposium on
Print_ISBN
978-1-4799-6964-7
Type
conf
DOI
10.1109/ISED.2014.35
Filename
7172762
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