Method to Determine Contrariety between Architectures Containing Stratified Memory Mapped Register Sets

As silicon architectures get more and more complex, the cost of development has scaled exponentially. IC design and embedded software are significant contributors to the overall cost of development. To enable cost effective solutions, the most commonly used approach is to define a platform with a family of devices to address different market segments. This approach will enable hardware and software reuse. The major impediment in this approach is the lack of any single metric to quantify the extent of compatibility across the family of devices. This paper presents a novel method for producing detailed summary to understand the degree of architecture incompatibility. This method uses machine-readable specifications created for family of devices and provides extensive register, bit-field and enumeration level differences between the two architectures to articulate the effort involved for software development and migration. This method has been used to determine architecture incompatibility for a derivative device spun off from a platform device, and was found to be 34% incompatible.