Title :
A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC
Author :
Bekal, Anush ; Goswami, Manish ; Singh, B.R. ; Pal, D.
Author_Institution :
Dept. of Microelectron., Indian Inst. of Inf. Technol. (IIIT-A), Allahabad, India
Abstract :
This paper instigates a "design of an 8-bit Asynchronous-Successive Approximation Register (ASAR) ADC (analog-to-digital converter) employing a Charge Scaling DAC (digital-to-analog converter)". The design itemizes the word asynchronous, which claims it to be independent of the external clock signal. The proposed design is composed of a Comparator, Charge Scaling DAC and a digital SAR logic block. The design was simulated using 180nm CMOS technology and operated on a single 1 V power supply which dissipated a power of 32.419μW which is much lesser compared to the other existing architecture such as current scaling DAC and voltage scaling DAC.
Keywords :
CMOS integrated circuits; analogue-digital conversion; clocks; comparators (circuits); digital-analogue conversion; flip-flops; 8-bit ASAR ADC design; CMOS technology; analog-to-digital converter; asynchronous-successive approximation register; charge scaling DAC; clock signal; comparator; complementary metal oxide semiconductor; digital-to-analog converter; power 32.419 muW; size 180 nm; successive approximation register; voltage 1 V; word length 8 bit; Approximation methods; Arrays; CMOS integrated circuits; Capacitors; Clocks; Logic gates; Registers; ASAR ADC; Split Capacitive DAC; Successive Approximation (SA); analog-to-Digital converter; low power;
Conference_Titel :
Electronic System Design (ISED), 2014 Fifth International Symposium on
Print_ISBN :
978-1-4799-6964-7
DOI :
10.1109/ISED.2014.55
