Implementation of Area Efficient Hybrid MBIST for Memory Clusters in Asynchronous SoC

Author

Shirur, Yasha Jyothi M. ; Lakshmi, H.R. ; Chakravarthi, Veena S.

Author_Institution

ECE, BNMIT, Bangalore, India

fYear

2014

Firstpage

226

Lastpage

227

Abstract

In current scenario, asynchronous MPSoC are of great demand owing to their power efficiency. As the design flow is getting redefined for the design of asynchronous MPSoC, test methodology needs review and redefinition. The heterogeneous memories operating at different frequencies are an integrated part of Asynchronous MPSoC. And BIST controllers with separate MBIST schemes are traditionally used to test each of these memories. This paper deals with an area efficient Hybrid MBIST controller implemented to test multiple memories in an Asynchronous SoC. The work has resulted in lesser area solution to the extent of 60% when compared with the conventional scheme. Also, the percentage of reduction increases if the number of memories increases in the design.

Keywords

built-in self test; integrated circuit testing; integrated memory circuits; system-on-chip; area efficient hybrid MBIST controller; asynchronous MPSoC; heterogeneous memory; memory built-in self test; memory cluster; multiple memory testing; multiprocessor system on chip; power efficiency; Algorithm design and analysis; Circuit faults; Generators; Memory management; Multiplexing; System-on-chip; Testing; Asynchronous SoC; Hybrid MBIST; MARCH Algorithms; Multi Processor SoC; Multiple Memory Testing; Multiple Test Algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic System Design (ISED), 2014 Fifth International Symposium on

Print_ISBN

978-1-4799-6964-7

Type

conf

DOI

10.1109/ISED.2014.57

Filename

7172784