Title : 
Transistors for VLSI, for wireless: A view forwards through fog
         
        
            Author : 
Rodwell, M.J.W. ; Huang, C.-Y. ; Rode, J. ; Choudhary, P. ; Lee, S. ; Gossard, A.C. ; Long, P. ; Wilson, E. ; Mehrotra, S. ; Povolotskyi, M. ; Klimeck, G. ; Urteaga, M. ; Brar, B. ; Chobpattanna, V. ; Stemmer, S.
         
        
            Author_Institution : 
ECE Depts., Univ. of California, Santa Barbara, Santa Barbara, CA, USA
         
        
        
        
        
            Abstract : 
Summary form only given. For VLSI, transistors are made small, making them plentiful (cheap) and the wires connecting them short, with low delay (CVDD/I), and low switching energy (CVDD2/2); small-area electronics is key. Low power demands low VDD yet low Ioff . Below threshold, we seek characteristics steeper than thermal; above it, dI/dV should be large. Tunnel FETs [1] are the most studied steep transistors. Yet, in nm TFETs, quantization increases barrier energies and nonparabolicy increases carrier mass. WKB hand calculations predict only 10% tunneling probability for a 2nm barrier, 1% for 4nm. The barrier thickness is not easily reduced, being set by the source doping and channel and dielectric thicknesses, hence on-current and logic speed will be low. Adding a second barrier [2] introduces a bound state, and dI/dV peaks as the state aligns with the source. A multi-layer electron anti-reflection coating (fig.1) [3], increases transmission over a broad energy range; design parallels microwave impedance-matching.
         
        
            Keywords : 
VLSI; antireflection coatings; field effect transistors; impedance matching; microwave integrated circuits; probability; semiconductor doping; tunnel transistors; TFET; VLSI transistors; WKB hand calculation; barrier energy; low delay; low switching energy; microwave impedance matching; multilayer electron antireflection coating; size 2 nm; small-area electronics; source doping; steep transistors; tunnel FET; tunneling probability; Dielectrics; Logic gates; MOSFET; Tunneling; Very large scale integration;
         
        
        
        
            Conference_Titel : 
Device Research Conference (DRC), 2015 73rd Annual
         
        
            Print_ISBN : 
978-1-4673-8134-5
         
        
        
            DOI : 
10.1109/DRC.2015.7175529