Cache for Flow Content: Solution to dependent packet processing in FPGA

Perpetual demand for bandwidth, fueled by the rapid growth of data and multimedia contents, calls for ever-faster packet processing capability in network infrastructure. For management and security reasons, packet flow information are sometimes stored, thus pushing the adoption of flow buffering techniques in various scenarios, e.g., in the architecture of FPGA with DDR SDRAM attached. Unfortunately, as the gap between two packets from the same flow shortens, latter packet write operation on SDRAM may probably neglects the former one, causing wrong flow state, just like the case of data hazard in CPU instruction pipeline. This paper analyzes the relationship between cache quantity and packet processing pipeline, exploring the organization of caches, and then a practical Cache for Flow Content (CFC) memory is proposed to solve the above-mentioned packet dependency problem.