Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems

Author

Kol, Rakefet ; Ginosar, Ran ; Samuel, Goel

Author_Institution

Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel

fYear

1996

Firstpage

164

Lastpage

174

Abstract

We apply a novel methodology, based on statecharts, for the design of large scale asynchronous systems. The EXV CAD tool offers specification at multiple levels, simulation, animation, and compilation into synthesizable VHDL code. EXV has some verification capabilities, and we add a validation sub-system EXV is originally synchronous, but we discuss how to employ it for asynchronous design. The tool is demonstrated through a simple FSM

Keywords

asynchronous circuits; logic CAD; EXV CAD tool; FSM; asynchronous design; large scale asynchronous systems; specification; statecharts; Animation; Circuit synthesis; Clocks; Design automation; Design methodology; Hardware; Large-scale systems; Radio access networks; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on

Print_ISBN

0-8186-7298-6

Type

conf

DOI

10.1109/ASYNC.1996.494448

Filename

494448

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3600157