Design guidelines to achieve a very high ESD robustness in a self-biased NPN

In this paper, using extensive TCAD simulations and measurement results, we analyze the basic mechanisms involved during an ESD stress in a self-biased NPN bipolar transistor used as an ESD protection. From the deep understanding of these mechanisms, we define design guidelines to achieve a very high ESD robustness (=10kV) in this type of device. These guidelines are validated on several CMOS technologies.