Title :
Superior switching behaviour of BIMOS transistor in Darlington/parallel combination
Author :
Thakur, D.K. ; Kumar, A. ; Vyas, P.D. ; Khokle, W.S.
Author_Institution :
Central Electron. Eng. Res. Inst., Pilani, India
Abstract :
A lateral DMOS merged bipolar transistor, LDBIMOST, in Darlington/parallel combinations has been fabricated using a high resistivity p-substrate to handle large currents with superior speed. LDBIMOST has the same structure as a lateral double-diffused MOS transistor (LDMOST) with p-body as a base of an active npn bipolar transistor. The device has been modelled using process and device computer programs and a circuit simulator to optimize the design to obtain a high breakdown voltage, low Ron and parasitic-free monolithic merged LDMOS bipolar structure. The influence of gate potential and gate metal over the drift-region on Ron has been investigated. Several LDMOS test structures with varying channel width have been designed to study electrical performance. It has been revealed that an additional integration of LDMOST along with an LDBIMOS transistor on the same chip with the minimum area concept has improved the turn-off speed of the device from 490 ns to 270 ns at a current level of 1.3 Amp
Keywords :
bipolar transistors; insulated gate field effect transistors; power transistors; semiconductor device models; semiconductor process modelling; semiconductor switches; 1.3 A; 270 ns; BIMOS transistor; Darlington/parallel combination; LDBIMOST; active npn bipolar transistor; channel width; circuit simulator; device model; gate metal; gate potential; high breakdown voltage; high resistivity p-substrate; lateral DMOS merged bipolar transistor; minimum area concept; on-resistance; parasitic-free monolithic merged LDMOS bipolar structure; process model; switching behaviour; turn-off speed;
Conference_Titel :
Power Electronics and Applications, 1993., Fifth European Conference on
