DocumentCode
3600523
Title
A study of CMOS 2.0V low power pager receiver for the FLEXTMpaging system
Author
Takada, Toshio ; Suzuki, Yuki ; Tanaka, Satoshi ; Nagai, Kenji
Author_Institution
Kokusai Electric Co., Sendai, Japan
fYear
1998
Firstpage
376
Lastpage
379
Abstract
The 0.4µm CMOS receiver IC for the FLEXTMpaging system is designed and fabricated to integrate analog and digital building blocks onto a single chip in the near future. To study the influences of the digital switching noise into analog building blocks, a digital noise source block is implemented with the receiver IC. The receiver IC contains a 2nd mixer, a limiting amplifier, a detector, base-band amplifiers and a bit rate filter, and satisfies the specification of the FLEXTMpaging systems. The receiver IC consumes 2.8mW(1.4mA × 2.0V) in the receiving mode.
Keywords
Analog integrated circuits; Band pass filters; CMOS integrated circuits; Detectors; Digital integrated circuits; Frequency shift keying; Image converters; Integrated circuit noise; Power dissipation; Radiofrequency amplifiers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
Type
conf
DOI
10.1109/ESSCIR.1998.186287
Filename
1471044
Link To Document